IC (memory/microprocessor/logic ICs, analog ICs)

Hinomaru FPGA (no.1) FeRAM based FPGA

An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead. In this booth, we show the chip that we developed a reconfigurable logic chip based on FeRAM (Ferroelectric random access memory) technology. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (Non-Volatile FlipFlop), which contains FeRAM, a FF, and power-gating control circuits, is used as configuration memory. The NV-FF can transmit data between FeRAM and FF automatically when power to the chip is turned off/on. Thus, chip-level power gating is possible.

Research results:
M.Iida, M.Koga, K.Inoue, M.Amagasaki, Y.Ichida, M.Saji, J.Iida and T.Sueyoshi
"A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells",
IEICE Transactions on Electronics, Vol.E94-C, No.4, pp.548-556 ,Apr. 2011

IC (memory/microprocessor/logic ICs, analog ICs)

Hinomaru FPGA (no.2) FT-FPGA

We have studied FT-FPGA(Fault-Tolerant Field Programmable Gate Array) architectures and their design framework for IP(Intellectual Property) cores in SoC(System on Chip). Like a discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault voidance, and a configuration mechanism for single-cycle reconfiguration. Traditional ASIC(Application Specific Integrate Circuit) tools can also treat FT-FPGA directly in design phase.

Research results:
M.Amagasaki, Kazuki Inoue, Q.Zhao, M.Iida, M.Kuga and T.Sueyoshi,
`` DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI,''
Proc. of 23th International Conference on Field Programmable Logic and Applications (FPL2013), porto, porutugal, Sep. 2013.

Hardware design solutions

Self-recovery dependable system

FPGAs are widely employed as the development platform in various embedded systems, therefore, the dependability of FPGA devices are becoming more and more important today. We are researching on dependable system that consists of SRAM based FPGA, particularly on the problems of radiation caused soft-error and accident caused hard-error. For the soft-error, the proposed soft-core processor can automatically synchronize internal context and recover to normal state as soon as soft-errors are detected. For the hard-error avoidance, the user circuit on the damaged modules can be switched to spare modules with partial reconfiguration.

Research results:
Y.Ichinomiya, S.Usagawa, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi,
``Designing flexible reconfigurable regions to relocate partial bitstreams,''
Proc. the 20th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2012), pp.241, Toronto, Canada, May 2012

Y.Ichinomiya, T.Ishida, S.Tanoue, M.Amagasaki, M.Kuga, T.Sueyoshi
``Reliable Softcore Processor Using Partial Reconfiguration Technique for SRAM-Based FPGA,''
IEICE Trans on Infomation and systems (Japanese Edition), vol.J92-D, no.12, pp.2105-2113, Dec. 2009.